This invention relates to methods of fabricating microelectronic devices, to integrated circuits, and to intermediate constructions of integrated circuits.
When fabricating microelectronic devices, integrated circuits, and the like, successive layers of various materials are often formed over a substrate and portions of such materials are removed to yield the desired device features. Generally, only the first few layers are deposited on a completely planar surface. Thereafter, fabrication of device features begins and successive layers are formed over features and/or portions of the substrate of varying topography. Such changes in topography may be referred to as steps, gaps, lines, etc. Layers of material subsequently formed over such features may be said to possess a horizontal portion, generally parallel to the original planar substrate, and a vertical portion, generally perpendicular to the original planar substrate. Anisotropic, or directional, etching of such subsequent layers often is ineffective in completely removing the vertical portion of such layers. Accordingly, frequently a horizontal portion of a layer may be almost entirely removed while the vertical portion is largely unaffected. Essentially, such processing leaves a residual wall formed from the remaining vertical portion of the layer.
In some circumstances, the residual wall must be removed to yield the desired structure. For example, when forming conductive lines it is common to deposit a layer of barrier material over varying topography to protect against chemical reaction or diffusion. Thereafter, a layer of conductive material is formed. The two layers of material are then patterned to remove unwanted portions and leave behind a pattern of conductive lines comprising the barrier material and the overlying conductor. Anisotropic etching is often used to remove the undesired material. Unfortunately, a residual wall of one or both of the two layers is often left behind as a vertical portion of such layers. In this context, such residual walls may be referred to as shorting stringers. Such shorting stringers extend between conductive lines, resulting in electrical shorts. Accordingly, additional effort may be undertaken to remove shorting stringers and to avoid defects resulting therefrom.
In other circumstances, residual walls from a vertical portion of a layer may be used to an advantage. An edge defined feature (EDF) is a material that remains as a residual wall after anisotropic etching. The width of an EDF may be controlled by selecting the thickness of the deposited layer from which it resulted. The height of an EDF may be controlled by the height of the feature over which it was formed to yield the vertical portion. Accordingly, an EDF may be sublithographic. The original feature on which an EDF is formed may subsequently be removed to yield a freestanding EDF. The original feature essentially may act as a core around which the EDF is shaped and may be referred to as a mandril.
Despite the advantages of an EDF, there remain difficulties in processing. For example, generally it is not desired that every vertical portion remaining after anisotropic etching of a deposited layer function as an EDF. Accordingly, a subsequent mask of intended EDFs and etching of undesired vertical portions is required.
It would be an improvement in the art if the mask and etch step required to fully define an EDF could be eliminated, simplifying the formation process. It would also be an improvement to remedy the problem of shorting stringers or other residual walls that remain after anisotropic etching. Unless such difficulties are resolved, the processing methods described above will continue to require additional process steps to address such residual material.
In accordance with an aspect of the invention, a microelectronic device fabricating method includes providing a substrate having a beveled portion, forming a layer of structural material on the beveled portion, and removing some of the structural material from the beveled portion by anisotropic etching to form a device feature from the structural material. By way of example, only a portion of the structural material may be removed from the beveled portion such that a device feature is formed on the beveled portion. Such a device feature may include a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Also, an effective amount of the structural material may be removed from the beveled portion while remaining structural material forms an edge defined feature.
According to another aspect of the invention, an integrated circuit includes a semiconductive substrate, a layer of dielectric material over the substrate having a beveled edge, and a pair of spaced, adjacent, chemical reaction or diffusion barrier material lines. The lines extend over the beveled edge and are substantially void of residual shorting stringers.
In accordance with yet another aspect of the invention, an intermediate construction of an integrated circuit includes a semiconductive substrate and a raised mandril over the substrate. The mandril has a beveled edge and an edge substantially perpendicular to the substrate. A layer of structural material forms an edge defined feature on the perpendicular edge.
Other aspects of the invention may be apparent from the detailed description of preferred embodiments below.